In the field of CMOS (complementary metal-oxide semiconductor) fabrication, split gates semiconductor devices are formed having control and select gates. Current lithography processes used to form the control and select gates lead to misalignment of the gates, which results in undesirable threshold voltage distributions. Furthermore, the lithography processes used require three lithography processes to form the two gates. For each lithography process, a different mask is needed. This increases costs and the repeated steps increase manufacturing cycle time. Thus, a process for preventing these adverse effects when forming split gates having control and select gates is desired.
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